1. Field of the Invention
This invention relates to a clock recovery circuit and, more particularly, to a phase-locked loop (“PLL”) circuit having a linear phase detector and voltage controlled oscillator that will sample received data patterns at a reduced clock rate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Modern high-speed data communication systems typically use internal clock-referenced circuitry. The circuitry is designed to synchronize with, for example, an incoming data stream or reference signal. In most instances, a PLL circuit is used to derive a clock from an incoming data stream and provide that clock for use by clock-referenced circuitry.
In its most basic form, a PLL consists of a phase/frequency detector, a filter, control circuitry, and a variable oscillator. In a clock recovery application, output from the oscillator constitutes a recovered clocking signal whose frequency and phase are compared against an incoming data stream. Thus, the clocking signal preferably oscillates at a rate based upon sampling edge transitions of an incoming data stream. Once compared, the control circuitry adjusts the oscillator output frequency so that the incoming data stream and the oscillator output are transitioning at, ideally, the same frequency and phase with one another.
A substantial amount of work with PLLs involves the design and implementation of the phase detectors. There are two types of phase detectors: linear and non-linear. FIG. 1 illustrates gain characteristics of a non-linear phase detector 10 and a linear phase detector 12. As shown, a linear phase detector 12 will exhibit gain characteristics that are proportional to the phase error between the oscillator output and the incoming data stream. As the input phase error difference increases or decreases, the linear phase detector that drives a charge pump will exhibit an average output current or voltage that will also increase or decrease linearly. The linear relationship between the relative pump up and pump down outputs from the phase detector are based upon the linear phase differences at the inputs that can generally be used to generate average error correction signals within the PLL. The linear phase detector charge pump gain is based upon a mathematical model that can predict fairly well the average output error signal generated based upon the relative input phase differences between two clock signals within a negative and a positive range in time. In other words, for each point in which the feedback-clocking signal lags or leads the incoming data stream, a prediction can be easily made through modeling on what will be the appropriate pump up and pump down duty cycles. These error signals can be used to generate currents or voltages that in turn control the oscillator sampling clock.
Conversely, non-linear phase detectors theoretically have an infinite gain at the phase-lock point and this gain is somewhat non-deterministic around the phase-lock point and is typically hard to guarantee. Obtaining mathematical descriptions and models, other than rough approximations, that describe a non-linear loop dynamic are rarely published and difficult to obtain. In this scenario, the actual PLL design process can become one of a very empirical nature. As shown in the non-linear example 10, slight changes in phase differences of the incoming clock feedback signals from a lock point will either drive the pump up/pump down ratio fully in the positive direction or fully in the negative direction. Thus, certain types of non-linear phase detectors are referred to as a “bang-bang” or “early-late” phase detectors. In a bang-bang phase detector, slight error differences at the inputs to the phase detector will drive the phase detector outputs to rail (i.e., “bang”) and will make no distinction between small or large input errors and phase differences. The large gain, and its variation over process, can unfortunately lead to PLL performance degradation. For example, in a SONET receiver application, these non-linear phase detector gain variations can change PLL bandwidth parameters that can ultimately lead to jitter peaking. This relative instability can skew over time with different data patterns along with semiconductor fabrication processing and operating temperature variations.
It would be advantageous to be able to easily produce a linear phase detector if it is deemed important to predict output for small perturbations of phase error or phase differences on the detector input. However, other forms of linear phase detectors can require a feedback-clocking signal that transitions at twice the frequency as the maximum input data stream. SONET bit streams can have a bit rate exceeding 10 Gbit/sec or even 40 Gbit/sec (e.g., SONET/SDH Standard OC-192 specifies a transmission rate of 9953.28 Mbit/sec, and OC-768 specifies a transmission rate of 39813.12 Mbit/sec). Consequently, at the modern data transmission rates, deriving a voltage-controlled oscillator to transition at twice the incoming bit stream frequency is difficult. For example, a 40 Gbit/sec SONET data stream would require a 40 GHz voltage-controlled oscillator output, which is very hard to achieve with most current fabrication techniques.
Examples of linear phase detectors that require a feedback clocking signal at twice the maximum incoming data frequency are set forth in Hogge, “A Self Correcting Clock Recovery Circuit,” IEEE Jr. of Lightwave Technology, Vol. LT-3, December 1985; and, Lee, “A 155-MHz Clock Recovery Delay and Phase-Locked Loop,” IEEE Jr. of Solid-State Circuits, Vol. 27, No. 12, December 1992. The Hogge and Lee references describe the benefits of using linear phase detectors in a clock recovery application. Yet, however, in both references, a feedback-clocking signal is shown that transitions at twice the incoming maximum data rate frequency.
An unfortunate outcome of requiring a high-speed voltage-controlled oscillator output is not only the difficulty in designing and maintaining a high frequency VCO, but also the challenges presented in maintaining a linear response at high data rates. FIG. 2 illustrates a series of timing diagrams 14 from a phase detector whose output varies depending on the data rate input. More specifically, diagrams 14 indicate analog outputs that switch levels in a slew-rate limited manner based upon bandwidth limitations of the circuit operating frequency. The outputs integrate upward as the phase detector output goes positive and integrate downward as the phase detector output goes negative. The phase detector average output is, therefore, shown in its integrated form as having a sawtooth shape. As the data rate transition density increases (i.e., the number of 1s and 0s increases per second), the overall phase detector can exhibit a net decrease in gain due to this apparent pulse sliming and amplitude limiting consequence.
Waveforms 14 also illustrate additional non-linear pulse slimming attributed to phase offsets between the data and clock at a high data rate transfer density. As shown in waveform 14, an isolated error pulse is examined about the ideal lock-in point (zero phase error) and is identified as pulse 16b. The sampled phase error between data and clock can ultimately change where the leading edge of pulse 16 starts to transition from a low to high state, as shown by the variation of the nominal pulse width 16b increasing to 16a or decreasing to 16c. These effects will contribute to an asymmetric pulse width due to the signals switching in a slew-rate limit condition. Thus, pulses 16 further illustrate the phase detector gain limitations due to phase error pulse sliming that are attributed to pulse amplitude variation due to the varying phase error between data and clock at high data densities.
The effect upon the linear range and the overall linearity of the phase detector output, whenever gain characteristics change based on data dependency, is shown in graph 18. The output error pulse width and amplitude of the pulse of the pump up or pump down signal changes with the data input phase difference. Small phase differences tend to diminish the error pulse. If the error signals need to drive a charge pump, then this translates to loss of phase detector/charge pump gain, or no gain whatsoever. Linear range and phase detector gain over process variations will therefore be grossly effected. The results might be seen as induced PLL output clock jitter relative to the input data due to loss of gain. In another instance, a static phase offset of the data-sampling clock within the phase detector output can appear due to the lack of the phase detector being able to maintain adequate linear gain, thus contributing to bit-error rate degradation.
It would be desirable to introduce a clock recovery system that uses a PLL having a linear phase detector. It would also be desirable to derive a linear phase detector that does not require a feedback-clocking signal that transitions at twice the maximum frequency of the incoming data stream. An improved PLL with a phase detector operating at a relaxed sampling rate from a voltage-controlled oscillator would thereby extend the maximum operating frequency while avoiding the data dependent gain and jitter problems attributed to conventional linear phase detectors.